Maximum flexibility at TSMC: five production levels N3, N5 stacked from 2023

Image: TSMC

TSMC compensates for the three years of autonomy between the new nodes with new intermediate stages and greater flexibility, even at the transistor level. TSMC calls this the FinFlex approach, where customers can still prioritize area, performance, and power consumption at a given stage of production. There are countless possibilities.

N3 nodes in various versions

FinFlex will be based on a TSMC N3 process. Of these, the largest contract manufacturer in the world is now planning five variants: N3 as a basic version, which, however, will hardly be used. N3E, on the other hand, as an enhanced variant, the focus is completely on this level. It follows the classic N3P solution as a high performance variant and N3X as a high performance version and then the successor to N4X, which will not be available until next year, which means that N3X will be arriving late. And right in the middle, N3S is added as a special variant, the exact bonuses of this solution are unclear today, which is why there is not even a roadmap entry for it.

TSMC roadmap up to 2025
TSMC Roadmap to 2025 (Bild: TSMC)

Interesting are the references of TSMC today. The N3 core process is not selected in almost any diagram or on a slide, but always goes directly to N3E. It has long been rumored that TSMC struggled with the first version, both in terms of bonuses over previous processes and in performance. TSMC today stresses that the yield is “good” and production will begin at the end of the year. However, the N3E follows in just a few months with even higher performance or lower power consumption and better yields, which suggests that TSMC was unable to execute the plans it originally had, in terms of performance and time. Therefore, N3E is in fact the new base, even with respect to the next big process: N2 based on nanosheets aka Gate All Around.

N2 should continue the success story
N2 should continue the success story (Image: TSMC)

FinFlex for the best in performance, watts and area

TSMC also uses this N3E process to explain the new FinFlex implementation. Today’s chips are no longer built for just one purpose, but should be able to do many things. The new flexible implementations allow three different types of transistors to be used on a single die, so as not to use a complete compromise, but to help the respective sub-areas achieve their best performance or maximum savings.

FinFlex on TSMC's N3E process
FinFlex at TSMC’s N3E process (Image: TSMC)

The CPU cores, for example, are then produced with new 3-2 fins, the middle solution includes a 2-2 fin block, while at the lower end there is a 1-2 fin solution completely designed to save energy. According to TSMC, this combination also saves up to 23% of space compared to a normally implemented solution. A common design kit is designed to help customers quickly find and implement the best solution for them. A small video from TSMC explains it a bit.

A single nut with different fins
A single nut with different fins (Image: TSMC)
23 percent less space required
23% less space required (Image: TSMC)

Stacked N5 trial scheduled for 2023

TSMC has also provided an update on modern stack technologies. The media focus is on AMD’s 3D V-Cache solution, which will also be used in future Zen 4 processes. These were previously slated for 2023, TSMC now declares that the N5 process will then be ready for these solutions, the 3DFabric factory The newly built is expected to go into operation almost fully automatically in the second half of this year and will offer significantly more capacity than was available for the first generation. In April, when testing the AMD Ryzen R7 5800X3D with this technology, the editors came to the conclusion that this technology is here to stay.

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